Integrated circuits (ICs) comprise at least one core area configured to perform the active functions of the IC and at least one input/output (I/O) cell configured to transfer signals into and out of the core area. In some instances, the IC includes I/O cells connected to each side of the core area. That is, for a rectangular core area, the IC includes one I/O cell along each of the four sides of the perimeter of the core area. To facilitate scaling of technology nodes, gate used to form the at least one I/O cell and the at least one core area is restricted to a single lattice orientation. The single gate orientation; however, creates problems with the routing of conductive lines between elements of the at least one I/O cell.
In some instances, a conductive line for the at least one I/O cell is formed in a serpentine pattern to connect the elements of the I/O cell. The serpentine pattern is complicated and time consuming to form and increases the size of the I/O cell to accommodate turns in the conductive line. Thus, the serpentine pattern increases production cost and time due to the complexity of the pattern, and the decreased IC size afforded by the single gate orientation is partially offset by the increase in the size of the I/O cell. The serpentine pattern also causes difficulty in connecting the at least one core area to the I/O cell because a minimum space between the serpentine conductive line and a conductive pin configured to electrically connect the core area and the I/O cell is maintained to reduce the risk of short circuits. The serpentine conductive line pattern also exacerbates electrostatic discharge concerns, which may permanently damage the IC, in some instances.